| A-kind-of relation | 3.4 |
| A-part-of relation | 3.4 |
| Abstraction, see view |
| Acceleration |
| graphics | 9.2 |
| timed | 9.4 |
| Acoustic interference | 10.2 |
| Active component | 1.4 |
| Actor | 2.3 |
| Ada | 8.2 |
| Additive color space | 9.3 |
| Address unit (EBES) | E |
| Addressing, computer | 1.1 |
| Algebra, geometry | 3.6 |
| Algorithm |
| D | 6.5 |
| environment | 2.3 |
| greedy | 4.2 |
| ALI | 8.3 |
| Alignment | 4.4 |
| marks | 4.6 |
| Allocation, memory | 3.2 |
| An-instance-of relation | 3.4 |
| Analysis | 1.1 |
| dynamic | 5.1, 6.1 |
| functional verification | 5.5 |
| isolated-circuit detection | 5.4 |
| power estimation | 5.4, 6.5 |
| rule checking | 5.1, 5.3 |
| short-circuit detection | 5.4 |
| simulation | 5.1, 6.1, 11.5 |
| static | 5.1 |
| timing verification | 5.5 |
| tool | 1.1, 4.1 |
| transistor-ratio checking | 5.4 |
| verification | 5.1, 5.5 |
| And plane | 4.2 |
| Annotate (EDIF) | D |
| APL | 8.2 |
| Application-specific integrated circuit | 1.1 |
| Arc |
| EDIF | D |
| Electric | 11.2 |
| Gerber | A |
| invisible | 11.4 |
| object | 3.5 |
| universal | 11.4 |
| unrouted | 11.4 |
| Architect, machine | 2.1 |
| Array |
| gate | 4.2 |
| grid | 2.5 |
| reference (GDS II) | C |
| programmable logic | 4.2, 11.5 |
| storage/logic | 4.2 |
| uncommitted logic | 4.2 |
| Weinberger | 4.2 |
| Arraydefinition (EDIF) | D |
| Arrayrelatedinfo (EDIF) | D |
| Artificial intelligence | 1.1 |
| Artwork | 7.2 |
| alignment marks | 4.6 |
| compensation | 4.6 |
| critical dimensions | 4.6 |
| environment | 2.5, 11.4 |
| fiducial marks | 4.6 |
| pattern | 4.6 |
| scribe lane | 4.6 |
| target | 4.6 |
| technology (Electric) | 11.4 |
| ASIC, see application-specific integrated circuit |
| Aspect ratio | 9.3 |
| Asynchronous circuit | 1.3 |
| Attribute | 3.2 |
| Axiom | 2.3 |
| B-spline curve | 9.2 |
| Backtracking |
| constraint | 8.3 |
| routing | 4.3 |
| BASIC | 8.2 |
| Batch |
| change | 11.5 |
| integrated circuit | 7.3 |
| Behavior | 1.3 |
| EDIF view | D |
| -level simulation | 6.4 |
| Bezier curve | 9.2 |
| Bilevel display | 9.2 |
| Bipolar environment | 2.5, 11.4 |
| Bit-map, essential | 5.3 |
| Bitblt | 9.2 |
| Black box | 1.1 |
| Blending matrix | 9.2 |
| Block |
| transfer (BLT) | 9.2 |
| function | 1.2 |
| Boatload | 7.3 |
| Body (EDIF) | D |
| Bonding-machine format | 7.3 |
| Borderpattern (EDIF) | D |
| Boston geometry | 3.6 |
| Bottom-up |
| design | 1.2 |
| placement | 4.3 |
| programming | 8.1, 8.4 |
| Boundary (GDS II) | C |
| Bounding box | 1.2 |
| Box |
| black | 1.1 |
| bounding | 1.2 |
| CIF | B |
| GDS II | C |
| Branch-and-bound compaction | 4.2 |
| Branching factor | 1.2 |
| Bravo3 | 10.4 |
| Breadth-first search | 8.3 |
| Breshenham |
| circle | 9.2 |
| line | 9.2 |
| Bristle Blocks | 4.5 |
| Broadcast | 11.5 |
| Buffer, frame | 9.2 |
| Buried contact | 2.5 |
| C | 8.2, 11.1 |
| Cache, display | 9.2 |
| CAD (computer-aided design) | 1.1 |
| CADAT | 11.5 |
| CADDIF | 7.4 |
| Cadre | 4.5 |
| CAE (computer-aided engineering) | 1.1 |
| Caesar | 3.6, 10.4 |
| Call (CIF) | B |
| Calligraphic display | 9.2 |
| Caltech Intermediate Format, see format, CIF |
| Cell | 1.2 |
| composition | 1.2 |
| database | 8.4 |
| differentiation | 1.2 |
| EDIF | D |
| Electric | 11.2 |
| generation | 4.2 |
| leaf | 1.2 |
| library | 2.5 |
| overlap | 1.2 |
| parameterized | 1.2, 8.1 |
| procedural | 8.4 |
| root | 1.2 |
| standard | 2.5 |
| Change |
| batch | 11.5 |
| checkpoint | 10.4 |
| commit | 10.4 |
| database | 10.4 |
| undo | 3.2 |
| Channel | 4.3 |
| routing | 4.3 |
| -less gate-array | 4.2 |
| Character recognition | 10.4 |
| Checking |
| design rule | 5.3, 11.5 |
| rule | 5.1 |
| transistor-ratio | 5.4 |
| Checkpoint (see also change) | 10.4 |
| CIF, see format |
| Circle |
| Breshenham | 9.2 |
| EDIF | D |
| Gerber | A |
| Circuit |
| asynchronous | 1.3 |
| designer | 2.1 |
| feedback | 6.6 |
| integrated | 1.1 |
| -level simulation | 6.2 |
| printed | 1.1, 7.2 |
| synchronous | 1.3 |
| wire-wrap | 1.1 |
| Clipping | 9.2 |
| polygon | 9.2 |
| screen | 9.2 |
| Sutherland-Cohen | 9.2, 10.3 |
| Clock |
| nonoverlapping | 1.3 |
| skew | 1.3 |
| two-phase | 1.3 |
| Closed polygon | 9.2 |
| Cluster, memory | 3.2 |
| CMOS | 2.1, 2.5, 11.4 |
| Cognition, human | 10.2 |
| Color |
| additive space | 9.3 |
| EDIF | D |
| four-color | 9.3 |
| inversion | 9.3 |
| map | 9.2 |
| subtractive space | 9.3 |
| Command |
| completion | 10.4 |
| language | 8.2, 10.1, 10.4 |
| Commit | 10.4 |
| Compaction | 4.2 |
| branch-and-bound | 4.2 |
| Electric | 11.5 |
| fence | 4.2 |
| graph | 4.2 |
| one-dimensional | 4.2 |
| overconstraint | 4.2 |
| simulated annealing | 4.2 |
| track | 4.2 |
| Comparison, network | 5.2 |
| Compensation | 4.6 |
| Electric | 11.5 |
| negative | 4.6 |
| positive | 4.6 |
| Compiler, silicon | 1.1, 4.1, 4.5, 11.5 |
| Complex |
| component | 3.3 |
| prototype | 11.2 |
| Component |
| active | 1.4 |
| complex | 3.3 |
| -level environment | 2.4 |
| passive | 1.4 |
| primitive | 2.1, 3.3, 11.2 |
| representation | 3.5 |
| Composition |
| cell | 1.2 |
| rule | 1.4 |
| Computer |
| address space | 1.1 |
| -aided design | 1.1 |
| -aided engineering | 1.1 |
| Connection rule | 1.4 |
| Connectivity | 1.1, 1.4 |
| representation | 3.5 |
| Consistency in display/hardcopy | 9.3 |
| Constraint | 8.1 |
| backtracking | 8.3 |
| connectivity | 1.4 |
| design | 1.1 |
| Electric | 11.3 |
| fixed-angle | 11.3 |
| hierarchical-layout | 11.3 |
| linear inequality | 8.3, 11.3 |
| loop | 8.3 |
| overconstraint | 4.2, 8.3 |
| propagation | 8.3 |
| relaxation | 8.3 |
| representation | 3.2 |
| rigidity | 11.3 |
| sequencing | 8.3 |
| slidable | 11.3 |
| Contact |
| buried | 2.5 |
| cut | 2.5 |
| layer | 2.5 |
| Contents (EDIF) | D |
| Control |
| point | 9.2 |
| rule | 4.5 |
| Conversion, format | 7.4 |
| Core, SIGGRAPH | 9.1 |
| Corner stitching | 3.6 |
| Correspondence, view | 1.3 |
| Cosine | 9.2 |
| Crash recovery | 10.4 |
| Critical dimensions | 4.6 |
| Criticalsignal (EDIF) | D |
| Crosshair | 9.4 |
| Crystal | 5.5 |
| Cubic curve (Gerber) | A |
| Cursor | 9.4 |
| Curve |
| B-spline | 9.2 |
| Bezier | 9.2 |
| Breshenham | 9.2 |
| circular | 9.2 |
| control point | 9.2 |
| cubic | A |
| display | 9.2 |
| Gerber | A |
| Hermite | 9.2 |
| spline | 9.2 |
| D-algorithm | 6.5 |
| Daemon | 3.2, 8.1 |
| Daisy chain | 7.2 |
| Database |
| cell | 8.4 |
| change logging | 10.4 |
| conversion | 7.4 |
| modification | 3.2 |
| nonredundant | 3.6 |
| Dataflow |
| actor | 2.3 |
| environment | 2.3 |
| firing set | 2.3 |
| safe | 2.3 |
| DD (CIF) | 7.4, B |
| Declarative programming | 8.1, 8.3 |
| Define (EDIF) | D |
| Delay modeling | 6.5 |
| Depth-first search | 8.3 |
| Design |
| bottom-up | 1.2 |
| computer aided (CAD) | 1.1 |
| constraint | 1.1 |
| EDIF | D |
| environment | 1.1, 2.1 |
| frame | 7.4 |
| rule checking | 5.3 |
| Electric | 11.5 |
| hierarchical | 5.3 |
| polygon | 5.3 |
| raster | 5.3 |
| rule | 4.5 |
| syntactic | 5.3 |
| template | 5.3 |
| SLIC | 1.1, 2.3 |
| sticks | 1.1, 2.3 |
| top-down | 1.2 |
| virtual grid | 1.1, 2.3 |
| Designer |
| circuit | 2.1 |
| machine architect | 2.1 |
| mask | 2.1 |
| VLSI | 2.1 |
| Device model | 6.1, 6.2, 6.5 |
| DF (CIF) | B |
| Die | 7.3 |
| Differentiation, cell | 1.2 |
| Diffusion |
| layer | 2.5 |
| line tracing | 4.2 |
| Dimension |
| critical | 4.6 |
| two-and-one-half | 1.5 |
| Dimensionality | 1.1, 1.5 |
| DIP (dual inline package) | 2.5 |
| Direct method | 6.2 |
| Disk representation | 3.2 |
| Display |
| aspect ratio | 9.3 |
| bilevel | 9.2 |
| caching | 9.2 |
| calligraphic | 9.2 |
| hardcopy consistency | 9.3 |
| information | 10.1, 10.3 |
| list | 9.2 |
| monochrome | 9.2 |
| processor | 9.2 |
| raster | 9.2 |
| vector | 9.2 |
| Dithering | 9.3 |
| Document view (EDIF) | D |
| Dot (EDIF) | D |
| Doubly linked list | 3.2 |
| DPL | 8.2, 8.4 |
| DRC, see design rule checking |
| Drilling format | 7.2 |
| Drop |
| shadow | 9.2 |
| -in | 7.3 |
| DS (CIF) | B |
| Dual inline package (DIP) | 2.5 |
| Dualization | 4.3 |
| Dynamic analysis | 5.1, 6.1 |
| EARL | 8.3 |
| EBES, see format |
| Edge flag | 9.2 |
| EDIF, see format |
| Editing window | 10.3 |
| Electric | 2.5, 3.2, 4.2, 10.4, 11.1 |
| Electrical-rule checking (ERC) | 5.4 |
| Electron Beam Exposure System, see format, EBES |
| Electronic Design Interchange Format, see format, EDIF |
| Element (GDS II) | C |
| EMACS | 10.4 |
| Embedded language | 8.1 |
| End |
| drawing (EBES) | E |
| of block (EBES) | E |
| CIF | B |
| stripe (EBES) | E |
| Environment | 2.1 |
| algorithm level | 2.3 |
| artwork | 2.5, 11.4 |
| bipolar | 2.5, 11.4 |
| component level | 2.4 |
| dataflow | 2.3 |
| design | 1.1, 2.1 |
| Electric | 11.4 |
| flowcharting | 2.3 |
| GEM | 11.4 |
| generic | 11.4 |
| instruction-set processor (ISP) | 2.4, 4.5 |
| layout level | 2.5 |
| MOS | 2.1, 11.4 |
| object | 3.3 |
| PMS | 2.2 |
| pseudolayout | 2.3 |
| register transfer | 2.4 |
| schematic | 2.3, 11.4 |
| space | 2.1 |
| state diagram | 2.3 |
| sticks | 2.3 |
| system level | 2.2 |
| temporal logic | 2.3 |
| virtual grid | 2.3 |
| ERC (electrical rule checking) | 5.4 |
| Escher | 8.2 |
| ESIM | 11.5 |
| Essential bit-map | 5.3 |
| Etching layer | 4.2 |
| Event | 6.5 |
| Expert system | 4.5 |
| Exporting | 11.2 |
| External (EDIF) | D |
| Fabrication, mask | 4.6, 7.3 |
| Facet | 11.2 |
| Fan-in | 5.4 |
| Fan-out | 5.4 |
| Feedback |
| circuit | 6.6 |
| input device | 9.4 |
| user | 10.1, 10.5 |
| Fence | 4.2 |
| Fiducial marks | 4.6 |
| Field |
| -effect transistor | 2.5 |
| gravity | 10.4 |
| Figuregroup (EDIF) | D |
| Figuregroupdefault (EDIF) | D |
| Filled polygon | 9.2 |
| Fillpattern (EDIF) | D |
| Firing set | 2.3 |
| FIRST | 4.5 |
| Fitt's law | 10.4 |
| Fixed-angle constraint | 11.3 |
| Flag |
| edge | 9.2 |
| marking | 3.2 |
| Flat | 1.2 |
| Floating input | 5.4 |
| Floor |
| -plan, screen | 10.3 |
| -planning, see placement |
| Flowcharting | 2.3 |
| Folding | 4.2 |
| Font | 9.2 |
| Footprint | 1.2 |
| Format |
| bonding machine | 7.3 |
| CADDIF | 7.4 |
| CIF (Caltech Intermediate Format) | 7.3, 11.5, B |
| box | B |
| call | B |
| definition delete (DD) | 7.4, B |
| definition finish (DF) | B |
| definition start (DS) | B |
| end | B |
| layer | B |
| polygon | B |
| roundflash | B |
| user extensions | B |
| wire | B |
| conversion | 7.4 |
| disk | 3.2 |
| drilling | 7.2 |
| EBES (Electron Beam Exposure System) | 7.3, E |
| address unit | E |
| end drawing | E |
| end of block | E |
| end stripe | E |
| parallelogram | E |
| rectangle | E |
| start drawing | E |
| start stripe | E |
| stripe | E |
| trapezoid | E |
| EDIF (Electronic Design Interchange Format) | 7.3, 11.5, D |
| annotate | D |
| arc | D |
| arraydefinition | D |
| arrayrelatedinfo | D |
| behavior view | D |
| body | D |
| borderpattern | D |
| cell | D |
| circle | D |
| color | D |
| contents | D |
| criticalsignal | D |
| define | D |
| design | D |
| document view | D |
| dot | D |
| external | D |
| figuregroup | D |
| figuregroupdefault | D |
| fillpattern | D |
| global | D |
| gridmap | D |
| instance | D |
| instancemap | D |
| interface | D |
| joined | D |
| library | D |
| logicmodel | D |
| mask layout view | D |
| measured | D |
| member | D |
| multiple | D |
| mustjoin | D |
| netlist view | D |
| numberdefinition | D |
| orientation | D |
| path | D |
| pathtype | D |
| permutable | D |
| point | D |
| polygon | D |
| portimplementation | D |
| portmap | D |
| qualify | D |
| rectangle | D |
| rename | D |
| required | D |
| rotation | D |
| scale | D |
| scalex/y | D |
| schematic view | D |
| section | D |
| shape | D |
| signalgroup | D |
| simulate | D |
| status | D |
| step | D |
| stranger view | D |
| symbolic view | D |
| technology | D |
| timing | D |
| transform | D |
| translate | D |
| unused | D |
| view | D |
| viewmap | D |
| weakjoined | D |
| width | D |
| wire | D |
| written | D |
| GDS II | 7.3, 11.5, C |
| array reference | C |
| boundary | C |
| box | 7.4, C |
| element | C |
| library | C |
| node | 7.4, C |
| path | C |
| structure | C |
| structure reference | C |
| text | C |
| Gerber | 7.2, A |
| circular arc | A |
| cubic curve | A |
| line | A |
| parabolic curve | A |
| pen | A |
| preparatory function code | A |
| text | A |
| integrated circuit | 7.3 |
| interchange | 7.1 |
| manufacturing | 7.1 |
| numerically controlled (NC) drilling | 7.2 |
| printed-circuit | 7.2 |
| SDIF (Stimulus Data Interchange Format) | 7.4 |
| SHIFT | 7.3 |
| tester | 7.4 |
| wire-wrap | 7.2 |
| Formatting language | 8.2 |
| FORTRAN | 4.5 |
| Foundry |
| MOS Implementation Service (MOSIS) | 7.4 |
| silicon | 7.4 |
| Four-color | 9.3 |
| Frame |
| buffer | 9.2 |
| design | 7.4 |
| pad | 7.4 |
| Fully instantiated | 1.2 |
| Function block | 1.2 |
| Functional |
| hierarchical organization | 1.2 |
| -level simulation | 6.4 |
| verification | 5.5 |
| Garbage-collection | 3.2 |
| Gate |
| -array | 4.2 |
| channel-less | 4.2 |
| macro | 4.2 |
| -level simulation | 6.3 |
| matrix |
| generator | 4.2 |
| greedy algorithm | 4.2 |
| GDS II, see format |
| GEM environment | 11.4 |
| Generator |
| cell | 4.2 |
| external to cells | 4.3 |
| gate matrix | 4.2 |
| postlayout | 4.6 |
| programmable logic array | 4.2, 11.5 |
| regular forms | 4.2 |
| test vector | 5.1 |
| Geometric design-rule checking | 5.3, 11.5 |
| Geometry |
| algebra | 3.6 |
| Boston | 3.6 |
| Manhattan | 3.6 |
| representation | 3.6 |
| Gerber, see format |
| Gestalt | 9.3 |
| GKS | 9.1 |
| Global |
| EDIF | D |
| routing | 4.3 |
| Glyph | 10.3 |
| GPL | 8.2 |
| Graph |
| compaction | 4.2 |
| isomorphism | 5.2 |
| Graphics | 9.1 |
| accelerator | 9.2 |
| command language | 10.4 |
| mask | 4.6 |
| package | 9.1 |
| programming | 8.1 |
| representation | 3.6 |
| Gravity field | 10.4 |
| Greedy algorithm | 4.2 |
| Grid array | 2.5 |
| Gridmap (EDIF) | D |
| Hardcopy | 9.3 |
| Hardware-description language | 1.1, 8.2 |
| Hash table | 3.2 |
| Help | 10.4 |
| Hephaestus | 4.5 |
| Hermite curve | 9.2 |
| Heuristic | 1.1 |
| Hierarchy | 1.2 |
| branching factor | 1.2 |
| connectivity | 1.4 |
| design-rule checking | 5.3 |
| functional organization | 1.2 |
| layout constraints | 11.3 |
| organization | 1.2 |
| physical | 1.3 |
| representation | 3.3 |
| separated | 1.2 |
| spatial organization | 1.2 |
| structural | 1.1 |
| view | 1.3 |
| Hightower routing | 4.3 |
| History list | 3.2 |
| HPGL | 11.5 |
| Human |
| cognition | 10.2 |
| engineering | 10.1 |
| memory | 1.2 |
| motion | 10.2 |
| perception | 10.2 |
| I | 8.3 |
| IAGL | 8.2 |
| IC, see integrated circuit |
| Icarus | 10.3 |
| Icon | 10.3 |
| Iconic | 9.2 |
| ICPL | 8.2 |
| Idiomatic placement | 4.3 |
| Imperative programming | 8.1, 8.2 |
| Implant layer | 2.5 |
| Implementation service | 7.4 |
| Incremental-time simulation | 6.5 |
| Information display | 10.1, 10.3 |
| Input device | 9.4 |
| feedback | 9.4 |
| joystick | 9.4 |
| knob | 9.4 |
| light pen | 9.4 |
| mouse | 9.4 |
| spark pen | 9.4 |
| speech | 9.4 |
| tablet | 9.4 |
| thumbwheel | 9.4 |
| touch screen | 9.4 |
| tracker ball | 9.4 |
| valuator | 9.4 |
| Instance | 1.2 |
| EDIF | D |
| node | 11.2 |
| Instancemap (EDIF) | D |
| Instruction-set processor (ISP) | 2.4, 4.5 |
| Integrated circuit (IC) | 1.1 |
| batch | 7.3 |
| boatload | 7.3 |
| die | 7.3 |
| format | 7.3 |
| package | 2.4, 2.5 |
| run | 7.3 |
| wafer | 7.3 |
| Integration |
| large scale (LSI) | 2.5 |
| medium scale (MSI) | 2.5 |
| small scale (SSI) | 2.5 |
| tool | 11.5 |
| ultra large scale (ULSI) | 2.5 |
| very large scale (VLSI) | 2.5 |
| wafer scale (WSI) | 2.5 |
| Intensity resolution | 9.2 |
| Interchange |
| electronic design format see format, EDIF |
| format | 7.1 |
| stimulus data format | 7.4 |
| Interface |
| EDIF | D |
| user | 10.1, 11.5 |
| Interference |
| acoustic | 10.2 |
| semantic | 10.2 |
| Interval temporal logic | 2.3 |
| Invisible arc | 11.4 |
| Isolated-circuit detection | 5.4 |
| Isomorphism, graph | 5.2 |
| ISP (instruction-set processor) | 2.4, 4.5 |
| Jargon | 10.2 |
| Joined (EDIF) | D |
| Joystick | 9.4 |
| Junction transistor | 2.5 |
| Juno | 3.2, 8.3, 8.4 |
| Knob | 9.4 |
| L | 8.2 |
| Lambda | 3.6, 5.3 |
| Language |
| Ada | 8.2 |
| ALI | 8.3 |
| APL | 8.2 |
| BASIC | 8.2 |
| C | 8.2, 11.1 |
| command | 8.2, 10.1, 10.4 |
| graphics | 10.4 |
| textual | 10.4 |
| EARL | 8.3 |
| embedded | 8.1 |
| formatting | 8.2 |
| FORTRAN | 4.5 |
| GPL | 8.2 |
| hardware description | 1.1, 8.2 |
| I | 8.3 |
| IAGL | 8.2 |
| ICPL | 8.2 |
| L | 8.2 |
| LAVA | 8.3 |
| LISP | 7.3, 7.4, 8.2, 11.1, 11.3 |
| Mathematica | 11.1, 11.3 |
| picture | 8.2 |
| PL/I | 8.2 |
| Plates | 8.3 |
| PostScript | 9.3, 11.5 |
| Prolog | 11.3 |
| SILT | 8.3 |
| TCL | 11.1, 11.3 |
| Large-scale integration (LSI) | 2.5 |
| LAVA | 8.3 |
| Layer |
| buried | 2.5 |
| contact | 2.5 |
| CIF | B |
| diffusion | 2.5 |
| etching | 4.2 |
| implant | 2.5 |
| metal | 2.5 |
| native substrate | 2.5 |
| overglass | 2.5 |
| polysilicon | 2.5 |
| via | 2.5 |
| well | 2.5 |
| Layout |
| hierarchical constraint | 11.3 |
| -level environment | 2.5 |
| masklayout view, EDIF | D |
| pad | 4.3 |
| Leaf cell | 1.2 |
| Ledeen character recognizer | 10.4 |
| Lee-Moore routing | 4.3 |
| Library |
| cell | 2.5 |
| EDIF | D |
| Electric | 11.2 |
| GDS II | C |
| object | 3.3 |
| Light pen | 9.4 |
| Line |
| Breshenham | 9.2 |
| diffusion tracing | 4.2 |
| drawing | 9.2 |
| Gerber | A |
| Linear-inequality constraint | 8.3, 11.3 |
| Linked list | 3.2 |
| doubly | 3.2 |
| LISP | 7.3, 7.4, 8.2, 11.1, 11.3 |
| List |
| display | 9.2 |
| history | 3.2 |
| linked | 3.2 |
| Locality | 3.6 |
| Logging user input | 10.4 |
| Logic |
| interval temporal | 2.3 |
| -level simulation | 6.3 |
| random | 4.2 |
| temporal | 2.3 |
| uncommitted array | 4.2 |
| Logicmodel (EDIF) | D |
| Long-term memory | 10.2 |
| Loose routing | 4.3 |
| LSI (large-scale integration) | 2.5 |
| Lyra | 5.3 |
| Machine |
| architect | 2.1 |
| simulation | 6.7 |
| Macro | 1.2 |
| gate-array | 4.2 |
| package | 8.2 |
| Manhattan geometry | 3.6 |
| Manufacturing format | 7.1 |
| Map |
| color | 9.2 |
| essential bit | 5.3 |
| Marching menu | 10.3 |
| Marking | 3.2 |
| MARS | 11.5 |
| Mask |
| designer | 2.1 |
| fabrication | 7.3 |
| graphics | 4.6 |
| layout view, EDIF | D |
| write | 9.2 |
| Master-slice | 4.2 |
| Matrix |
| blending | 9.2 |
| gate | 4.2 |
| personality | 4.2 |
| Maze routing | 4.3 |
| Measured (EDIF) | D |
| Medium-scale integration (MSI) | 2.5 |
| Member (EDIF) | D |
| Memory |
| allocation | 3.2 |
| cluster | 3.2 |
| human | 1.2 |
| long term | 10.2 |
| paging | 3.2 |
| read only | 4.2 |
| short term | 10.2 |
| Menu | 10.3 |
| marching | 10.3 |
| number | 10.4 |
| pop-up | 10.3 |
| pulldown | 10.3 |
| Message window | 10.3 |
| Metal |
| layer | 2.5 |
| migration | 5.4 |
| Metal oxide semiconductor, see MOS |
| Migration, metal | 5.4 |
| Military standard | 2.3 |
| Min-cut placement | 4.3 |
| Miss Manners | 4.5 |
| Mixed-mode simulation | 6.4 |
| Mode | 10.4 |
| Model |
| delay | 6.5 |
| device | 6.1, 6.2, 6.5 |
| task | 10.1, 10.2 |
| user | 10.1, 10.2 |
| Module | 1.2 |
| Möire pattern | 9.2 |
| Monochrome display | 9.2 |
| MOS | 2.1 |
| CMOS | 2.1, 2.5, 11.4 |
| environment | 11.4 |
| nMOS | 2.1, 2.5, 11.4 |
| MOSIS | 7.4 |
| MOSSIM | 11.5 |
| Motion |
| human | 10.2 |
| pen | 9.3 |
| Mouse | 9.4 |
| optical | 9.4 |
| MSI (medium-scale integration) | 2.5 |
| Multidesigner circuits | 1.2 |
| Multilayer routing | 4.3 |
| Multilevel simulation | 6.4 |
| Multiperson project | 3.3 |
| Multiple |
| EDIF | D |
| -state simulation | 6.3 |
| -wire routing | 4.3 |
| Mustjoin (EDIF) | D |
| Native substrate layer | 2.5 |
| NC (numerically controlled drilling) | 7.2 |
| Negative compensation | 4.6 |
| Net | 1.4 |
| Netlist | 1.4 |
| EDIF view | D |
| Network | 1.4 |
| comparison | 5.2 |
| maintenance (Electric) | 11.5 |
| resistive | 4.3 |
| NEWSWHOLE | 10.5 |
| NMOS | 2.1, 2.5, 11.4 |
| Node |
| Electric | 11.2 |
| extraction | 1.4, 5.2, 6.5 |
| polygon | 5.2 |
| raster | 5.2 |
| GDS II | C |
| instance | 11.2 |
| object | 3.5 |
| prototype | 11.2 |
| Nonoverlapping clock | 1.3 |
| Nonredundant database | 3.6 |
| NS | 8.2, 8.4 |
| Number |
| menu | 10.4 |
| wheel | 10.4 |
| winding | 3.6 |
| Numberdefinition (EDIF) | D |
| Numerically controlled (NC) drilling format | 7.2 |
| Object | 3.2 |
| arc | 3.5, 11.2 |
| environment | 3.3 |
| library | 3.3, 11.2 |
| marking | 3.2 |
| node | 3.5, 11.2 |
| port | 3.5, 11.2 |
| prototype | 11.2 |
| technology | 11.2, 11.4 |
| tool | 11.2 |
| Obstacle | 4.3 |
| Obstruction | 4.3 |
| One-dimensional compaction | 4.2 |
| Opened polygon | 9.2 |
| Optical |
| character recognition | 10.4 |
| mouse | 9.4 |
| Or plane | 4.2 |
| Orientation |
| EDIF | D |
| restriction | 3.6 |
| Overconstraint | 8.3 |
| compaction | 4.2 |
| Overglass layer | 2.5 |
| Overlap, cell | 1.2 |
| Package |
| dual inline (DIP) | 2.5 |
| graphics | 9.1 |
| integrated circuit | 2.4, 2.5 |
| macro | 8.2 |
| pin grid array | 2.5 |
| polygon | 3.6 |
| quad | 2.5 |
| single inline (SIP) | 2.5 |
| Packaging | 7.3 |
| Pad |
| frame | 7.4 |
| layout | 4.3 |
| Paging memory | 3.2 |
| Painting | 1.4 |
| Palladio | 8.3 |
| Parabolic curve (Gerber) | A |
| Parallelogram (EBES) | E |
| Parameterized cell | 1.2, 8.1 |
| Parity scan | 9.2 |
| Passive component | 1.4 |
| Path |
| EDIF | D |
| GDS II | C |
| Pathtype (EDIF) | D |
| Pattern |
| artwork | 4.6 |
| fill | 9.3 |
| möire | 9.2 |
| PC (printed circuit) | 1.1, 7.2 |
| Pen |
| light | 9.4 |
| motion | 9.3 |
| spark | 9.4 |
| writing (Gerber) | A |
| Perception, human | 10.2 |
| Permutable (EDIF) | D |
| Personality matrix | 4.2 |
| PHIGS | 9.1 |
| Photoplotter | 7.2 |
| Physical hierarchy | 1.3 |
| PI | 4.3 |
| Picture language | 8.2 |
| Pin |
| grid array | 2.5 |
| wire-wrap | 7.2 |
| Pitch matching | 4.4 |
| Pixel | 9.2 |
| PL/I | 8.2 |
| PLA, see programmable logic array |
| Placement | 4.3 |
| and routing | 4.3 |
| bottom-up | 4.3 |
| dualization | 4.3 |
| idiomatic | 4.3 |
| min-cut | 4.3 |
| resistive network | 4.3 |
| simulated annealing | 4.3 |
| Plates | 8.3 |
| PMS environment | 2.2 |
| Point (EDIF) | D |
| Polygon |
| CIF | B |
| clipping | 9.2 |
| closed | 9.2 |
| design-rule checking | 5.3 |
| drawing | 9.2 |
| edge flag | 9.2 |
| EDIF | D |
| filling | 9.2 |
| node extraction | 5.2, 6.5 |
| opened | 9.2 |
| package | 3.6 |
| parity scan | 9.2 |
| pattern fill | 9.3 |
| seed fill | 9.2 |
| Polysilicon layer | 2.5 |
| Pop-up menu | 10.3 |
| Port |
| Electric | 11.2 |
| object | 3.5 |
| Portimplementation (EDIF) | D |
| Portmap (EDIF) | D |
| Positive compensation | 4.6 |
| Postlayout generation | 4.6 |
| PostScript | 9.3, 11.5 |
| Power estimation | 5.4, 6.5 |
| Preparatory function code (Gerber) | A |
| Primitive |
| component | 2.1, 3.3 |
| prototype | 11.2 |
| Printed circuit (PC) | 1.1 |
| format | 7.2 |
| Procedural cell | 8.4 |
| Process technology, semiconductor | 1.1, 2.1 |
| Processor, display | 9.2 |
| Programmable logic array |
| and plane | 4.2 |
| Electric | 11.5 |
| folding | 4.2 |
| generation | 4.2 |
| or plane | 4.2 |
| personality matrix | 4.2 |
| splitting | 4.2 |
| Programming | 8.1 |
| adding | 8.1 |
| bottom-up | 8.1, 8.4 |
| declarative | 8.1, 8.3 |
| Electric | 11.3 |
| graphics | 8.1 |
| imperative | 8.1, 8.2 |
| textual | 8.1 |
| top-down | 8.1, 8.4 |
| Project, multiperson | 3.3 |
| Prolog | 11.3 |
| Propagation, constraint | 8.3 |
| Prototype | 3.2 |
| complex | 11.2 |
| object | 11.2 |
| node | 11.2 |
| primitive | 11.2 |
| Pseudolayout environments | 2.3 |
| Puck | 9.4 |
| Pulldown menu | 10.3 |
| Quad |
| package | 2.5 |
| tree representation | 3.6 |
| Qualify (EDIF) | D |
| QuickDraw | 11.5 |
| R-tree representation | 3.6, 11.2 |
| Race condition | 1.3 |
| Rand tablet | 9.4 |
| Random logic | 4.2 |
| Raster |
| design-rule checking | 5.3 |
| display | 9.2 |
| node extraction | 5.2 |
| scan | 5.2 |
| Ratio |
| aspect | 9.3 |
| checking | 5.4 |
| RC tree | 5.5, 6.5 |
| Read-only memory (ROM) | 4.2 |
| Recovery, crash | 10.4 |
| Rectangle |
| EBES | E |
| EDIF | D |
| Register transfer | 2.4 |
| Regular form generation | 4.2 |
| Relation |
| a-kind-of | 3.4 |
| a-part-of | 3.4 |
| an-instance-of | 3.4 |
| Relaxation |
| constraint | 8.3 |
| techniques | 6.2 |
| Rename (EDIF) | D |
| Representation | 3.1 |
| component | 3.5 |
| connectivity | 3.5 |
| corner stitching | 3.6 |
| disk | 3.2 |
| Electric | 11.2 |
| essential bit-map | 5.3 |
| geometry | 3.6 |
| graphics | 3.6 |
| hierarchy | 3.3 |
| quad-tree | 3.6 |
| R-tree | 3.6, 11.2 |
| shape | 3.6 |
| tree | 3.6 |
| view | 3.4 |
| winged-edge | 3.6 |
| wire | 3.5 |
| Required (EDIF) | D |
| Resistive network placement | 4.3 |
| Resolution |
| intensity | 9.2 |
| spatial | 9.2 |
| Restored signal | 5.4 |
| Rigidity constraint | 11.3 |
| River routing | 4.3 |
| RNL | 11.5 |
| ROM (read-only memory) | 4.2 |
| Root cell | 1.2 |
| Rotation (EDIF) | D |
| Roto-routing | 4.3 |
| Roundflash (CIF) | B |
| Routing | 4.3 |
| backtracking | 4.3 |
| channel | 4.3 |
| Electric | 11.5 |
| global | 4.3 |
| Hightower | 4.3 |
| Lee-Moore | 4.3 |
| loose | 4.3 |
| maze | 4.3 |
| multilayer | 4.3 |
| multiple wire | 4.3 |
| obstacle | 4.3 |
| obstruction | 4.3 |
| river | 4.3 |
| roto | 4.3 |
| simulated annealing | 4.3 |
| switchbox | 4.3 |
| RSIM | 6.5, 11.5 |
| Rule (see also design rule) |
| checking | 5.1 |
| design | 5.3, 11.5 |
| electrical | 5.4 |
| composition | 1.4 |
| connection | 1.4 |
| control | 4.5 |
| design | 4.5, 5.3 |
| Run, integrated circuit | 7.3 |
| Safety | 2.3 |
| SAM | 8.2 |
| Sawing | 4.6 |
| Scale (EDIF) | D |
| Schematic |
| capture | 2.3 |
| EDIF view | D |
| environment | 2.3, 11.4 |
| Screen clipping | 9.2 |
| Scribe lane | 4.6 |
| Scribing | 4.6 |
| Scroll-bar | 10.3 |
| Scrolling | 10.3 |
| SDIF (Stimulus Data Interchange Format) | 7.4 |
| Search |
| breadth-first | 8.3 |
| depth-first | 8.3 |
| spatial | 3.6 |
| Section | 1.2 |
| EDIF | D |
| Seed fill | 9.2 |
| Semantic interference | 10.2 |
| Semiconductor process technology | 1.1, 2.1 |
| Sequencing, constraints | 8.3 |
| Separated hierarchy | 1.2 |
| Shape |
| EDIF | D |
| representation | 3.6 |
| Sheet | 3.6 |
| SHIELD | 6.2 |
| SHIFT | 7.3 |
| Short |
| circuit detection | 5.4 |
| term memory | 10.2 |
| SIGGRAPH Core | 9.1 |
| Signal |
| restored | 5.4 |
| unrestored | 5.4 |
| Signalgroup (EDIF) | D |
| Silicon |
| compiler | 1.1, 4.1, 4.5, 11.5 |
| foundry | 7.4 |
| SILT | 8.3 |
| Simulate (EDIF) | D |
| Simulated annealing |
| compaction | 4.2 |
| placement | 4.3 |
| routing | 4.3 |
| Simulation | 5.1, 6.1 |
| behavioral level | 6.4 |
| circuit level | 6.2 |
| Electric | 11.5 |
| event | 6.5 |
| functional level | 6.4 |
| gate level | 6.3 |
| incremental time | 6.5 |
| logic level | 6.3 |
| machines | 6.7 |
| mixed mode | 6.4 |
| multilevel | 6.4 |
| multiple state | 6.3 |
| switch level | 6.3 |
| timing | 6.5 |
| Sine | 9.2 |
| Single inline package (SIP) | 2.5 |
| Sketchpad | 3.2, 8.3 |
| Skew, clock | 1.3 |
| SLIC design | 1.1, 2.3 |
| Slice, master | 4.2 |
| Slidable constraint | 11.3 |
| Small-scale integration (SSI) | 2.5 |
| Socket | 7.2 |
| Space |
| color | 9.3 |
| computer address | 1.1 |
| environment | 2.1 |
| Spark pen | 9.4 |
| Spatial |
| dimensionality | 1.5 |
| hierarchical organization | 1.2 |
| resolution | 9.2 |
| search | 3.6 |
| Speech input | 9.4 |
| SPICE | 5.5, 7.4, 11.5 |
| Spline curve | 9.2 |
| Splitting | 4.2 |
| SSI (small-scale integration) | 2.5 |
| Standard cell | 2.5 |
| Start |
| drawing (EBES) | E |
| stripe (EBES) | E |
| State diagram | 2.3 |
| Static analysis | 5.1 |
| Status (EDIF) | D |
| Step (EDIF) | D |
| Sticks |
| design | 1.1 |
| environment | 2.3 |
| Stimulus Data Interchange Format (SDIF) | 7.4 |
| Storage/logic array | 4.2 |
| Stranger view (EDIF) | D |
| Stripe (EBES) | E |
| Structure |
| GDS II | C |
| hierarchy | 1.1 |
| reference, GDS II | C |
| Substrate layer | 2.5 |
| Subtractive color space | 9.3 |
| Sutherland-Cohen clipping | 9.2, 10.3 |
| Switch-level simulation | 6.3 |
| Switchbox | 4.3 |
| routing | 4.3 |
| Symbolic view (EDIF) | D |
| Synchronous circuit | 1.3 |
| Syntactic design-rule checking | 5.3 |
| Synthesis | 1.1, 4.1 |
| cell generation | 4.2 |
| diffusion-line tracing | 4.2 |
| expert system | 4.5 |
| gate matrix | 4.2 |
| gate-array | 4.2 |
| pad layout | 4.3 |
| placement | 4.3 |
| placement and routing | 4.3 |
| programmable-logic-array generation | 4.2, 11.5 |
| routing | 4.3, 11.5 |
| silicon compiler | 1.1, 4.1, 4.5, 11.5 |
| storage/logic array | 4.2 |
| tool | 1.1, 4.1 |
| Weinberger array | 4.2 |
| System |
| Bravo3 | 10.4 |
| Bristle Blocks | 4.5 |
| Cadre | 4.5 |
| Caesar | 3.6, 10.4 |
| DPL | 8.2, 8.4 |
| editing |
| EMACS | 10.4 |
| Electric | 2.5, 3.2, 4.2, 10.4, 11.1 |
| Escher | 8.2 |
| expert | 4.5 |
| FIRST | 4.5 |
| Hephaestus | 4.5 |
| Icarus | 10.3 |
| Juno | 3.2, 8.3, 8.4 |
| -level environment | 2.2 |
| Miss Manners | 4.5 |
| NEWSWHOLE | 10.5 |
| NS | 8.2, 8.4 |
| operating |
| TENEX | 10.4 |
| UNIX | 10.4 |
| Palladio | 8.3 |
| Polygon package | 3.6 |
| SAM | 8.2 |
| Sketchpad | 3.2, 8.3 |
| Talib | 4.5 |
| ThingLab | 3.2, 8.3 |
| Vexed | 4.5 |
| Table, hash | 3.2 |
| Tablet | 9.4 |
| puck | 9.4 |
| Rand | 9.4 |
| spark pen | 9.4 |
| Talib | 4.5 |
| Target, artwork | 4.6 |
| Task model | 10.1, 10.2 |
| Technology |
| EDIF | D |
| Electric | 11.4 |
| object | 11.2, 11.4 |
| semiconductor process | 1.1, 2.1 |
| Template, design-rule checking | 5.3 |
| Temporal | 1.3 |
| logic | 2.3 |
| interval | 2.3 |
| TENEX | 10.4 |
| Terminology | 10.2 |
| Test |
| format | 7.4 |
| inputs | 6.5 |
| vector | 5.1, 6.1 |
| Text |
| command language | 10.4 |
| drawing | 9.2 |
| GDS II | C |
| Gerber | A |
| programming | 8.1 |
| window | 10.3 |
| ThingLab | 3.2, 8.3 |
| Through hole | 7.2 |
| Thumbwheel | 9.4 |
| Tied outputs | 5.4 |
| Time | 6.1, 6.5 |
| stamp | 3.2 |
| Timed acceleration | 9.4 |
| Timing |
| EDIF | D |
| simulation | 6.5 |
| verification | 5.5 |
| Tool |
| analysis | 1.1, 4.1 |
| CADAT | 11.5 |
| Crystal | 5.5 |
| Electric | 11.5 |
| ESIM | 11.5 |
| integration | 11.5 |
| Lyra | 5.3 |
| MARS | 11.5 |
| MOSSIM | 11.5 |
| object | 11.2 |
| PI | 4.3 |
| RNL | 11.5 |
| RSIM | 6.5, 11.5 |
| SHIELD | 6.2 |
| SPICE | 5.5, 7.4, 11.5 |
| synthesis | 1.1, 4.1 |
| Tpack | 4.2, 8.2 |
| TV | 5.5 |
| Top-down |
| design | 1.2 |
| programming | 8.1, 8.4 |
| Topology | 1.1, 1.3 |
| Touch screen | 9.4 |
| Tpack | 4.2, 8.2 |
| Track | 4.2 |
| Tracker ball | 9.4 |
| Transform (EDIF) | D |
| Transformation | 3.6, 9.2 |
| Transistor |
| field effect | 2.5 |
| junction | 2.5 |
| ratio checking | 5.4 |
| Translate (EDIF) | D |
| Trapezoid (EBES) | E |
| Traveling-salesman | 4.3 |
| Tree |
| quad | 3.6 |
| R | 3.6 |
| RC | 5.5, 6.5 |
| representation | 3.6 |
| Turn | 11.5 |
| TV | 5.5 |
| Twisted-pair | 7.2 |
| Two-and-one-half-dimensional | 1.5 |
| Two-phase clock | 1.3 |
| Typeface | 9.2 |
| Ultra-large-scale integration (ULSI) | 2.5 |
| Uncommitted logic array | 4.2 |
| Undo | 3.2 |
| Universal arc | 11.4 |
| UNIX | 10.4 |
| Unrestored signal | 5.4 |
| Unrouted arc | 11.4 |
| Unused (EDIF) | D |
| User |
| extension (CIF) | B |
| input logging | 10.4 |
| interface | 10.1, 11.5 |
| model | 10.1, 10.2 |
| Valuator | 9.4 |
| Vector |
| display | 9.2 |
| test | 5.1, 6.1, 6.5 |
| Verification | 5.1, 5.5 |
| functional | 5.5 |
| timing | 5.5 |
| Very-large-scale integration (VLSI) | 1.1, 2.5 |
| Vexed | 4.5 |
| Via layer | 2.5 |
| View | 1.1, 1.3 |
| behavior | 1.3 |
| correspondence | 1.3 |
| EDIF | D |
| hierarchy | 1.3 |
| representation | 3.4 |
| temporal | 1.3 |
| topology | 1.3 |
| Viewmap (EDIF) | D |
| Virtual grid |
| design | 1.1 |
| environment | 2.3 |
| VLSI |
| chips | 1.1 |
| designer | 2.1 |
| Wafer |
| cutting | 4.6 |
| integrated circuit | 7.3 |
| scale integration | 2.5 |
| Weakjoined (EDIF) | D |
| Weinberger array | 4.2 |
| Well layer | 2.5 |
| Wheel |
| number | 10.4 |
| thumb | 9.4 |
| Width (EDIF) | D |
| Winding number | 3.6 |
| Window |
| editing | 10.3 |
| message | 10.3 |
| Winged-edge representation | 3.6 |
| Wire |
| CIF | B |
| EDIF | D |
| invisible | 11.4 |
| representation | 3.5 |
| universal | 11.4 |
| Wire-wrap | 1.1 |
| format | 7.2 |
| pin | 7.2 |
| socket | 7.2 |
| Wired-and | 1.4 |
| Wired-or | 1.4 |
| Write mask | 9.2 |
| Written (EDIF) | D |
| WSI (wafer-scale integration) | 2.5 |
| Yorktown simulation engine | 6.7 |
