Section 7 of 7

11.7 Summary

Electric is a workbench for the exploration of CAD algorithms. Because of its representational facilities, it can keep all kinds of information--much is already available. All the essential CAD system functions exist and are easily used. Thus node extraction and rasterization do not need to be implemented since the data are there. Input and output facilities are also available, as are powerful graphic display and editing. The CAD tool programmer needs to write only the inner loop of new code, and it can be easily plugged into the Electric framework. The system's powerful integration allows the addition of tools, environments, constraint systems, graphic interfaces, and much more.

Questions

1. Why is Electric's user interface not more tightly coupled with the database?
2. What is the difference between a complex node instance and a primitive node instance?
3. Where would you place information about the power dissipation of wires?
4. How can overconstrained situations arise in the hierarchical-layout constraint system?
5. During change broadcasts to tools in Electric, why can further changes not be made?
6. How can routing needs be specified graphically?

References

• Baker, Clark M. and Terman, Chris, "Tools for Verifying Integrated Circuit Designs," Lambda, 1:3, 22-30, 4th Quarter 1980.
• Batali, J. and Hartheimer, A., "The Design Procedure Language Manual," AI Memo 598, Massachusetts Institute of Technology, 1980.
• Bryant, Randal Everitt, A Switch-Level Simulation Model for Integrated Logic Circuits, PhD dissertation, Massachusetts Institute of Technology Laboratory for Computer Science, report MIT/LCS/TR-259, March 1981.
• Calma Corporation, GDS II Stream Format, July 1984.
• Electronic Design Interface Format Steering Committee, EDIF-Electronic Design Interchange Format Version 1 0 0, Texas Instruments, Dallas, Texas, 1985.
• Griswold, Thomas W., "Portable Design Rules for Bulk CMOS," VLSI Design, III:5, 62-67, September/October 1982.
• Guttman, Antonin, "R-Trees: A Dynamic Index Structure for Spatial Searching," ACM SIGMOD, 14:2, 47-57, June 1984.
• Harrison, D. S.; Moore, P.; Spickelmier, R. L.; and Newton, A. R., "Data Management and Graphics Editing in the Berkeley Design Environment," 1986 IEEE International Conference on Computer-Aided Design, 24-27, 1986.
• HHB, CADAT User's Manual, Revision 5.0, HHB-Softron, Mahwah, New Jersey, June 1985.
• Hon, Robert W. and Sequin, Carlo H., "A Guide to LSI Implementation," 2nd Edition, Xerox Palo Alto Research Center technical memo SSL-79-7, January 1980.
• Johnson, Stephen C., "Hierarchical Design Validation Based on Rectangles," Proceedings MIT Conference on Advanced Research in VLSI (Penfield, ed), 97-100, January 1982.
• Kernighan, Brian W. and Ritchie, Dennis M., The C Programming Language, Prentice-Hall, Englewood Cliffs, New Jersey, 1978.
• Kingsley, C., Earl: An Integrated Circuit Design Language, Masters Thesis, California Institute of Technology, June 1982.
• Kostiuk, A. R., "QUISC: An Interactive Silicon Compiler," M.Sc. Thesis, Queen's University at Kingston, Department of Electrical Engineering, 1987.
• Kroeker, Wallace I., Integrated Environmental Support for Silicon Compilation of Digital Filters, Masters Thesis, University of Calgary Computer Science Department, March 1986.
• Lansky, A. L. and Owicki, S. S., "GEM: A Tool for Concurrency Specification and Verification," Proceedings 2nd Annual ACM Symposium on Principles of Distributed Computing, 198-212, August 1983.
• Lipton, Richard J.; North, Stephen C.; Sedgewick, Robert; Valdes, Jacobo; and Vijayan, Gopalakrishnan, "ALI: a Procedural Language to Describe VLSI Layouts," Proceedings 19th Design Automation Conference, 467-473, June 1982.
• Lyon, Richard F. and Schediwy, Richard R., "CMOS Static Memory with a New Four-Transistor Memory Cell," Proceedings Stanford Conference on Advanced Research in VLSI (Losleben, ed), 111-132, March 1987.
• Mukherjee, Amar, Introduction to nMOS and CMOS VLSI Systems Design, Prentice-Hall, Englewood Cliffs, New Jersey, 1986.
• Nagel, L. W., "Spice2: A Computer Program to Simulate Semiconductor Circuits," University of California at Berkeley, ERL-M520, May 1975.
• Ousterhout, J. K., "Caesar: An Interactive Editor for VLSI Layouts," VLSI Design, II:4, 34-38, 1981.
• Rubin, Steven M., "An Integrated Aid for Top-Down Electrical Design," VLSI '83 (Anceau and Aas, eds), North Holland, Amsterdam, 63-72, August 1983.
• Serbin, B. M., "QUAIL: An Interactive, Mixed-Mode, Multi-State Hierarchical Logic Simulator," M.Sc. Thesis, Queen's University at Kingston, Department of Electrical Engineering, 1987.
• Singh N. "MARS: A Multiple Abstraction Rule-Based Simulator," Stanford University Heuristic Programming Project HPP-83-43, December 1983.
• Weste, Neil, "Virtual Grid Symbolic Layout," Proceedings 18th Design Automation Conference, 225-233, June 1981.
• Williams, John D., "STICKS-A graphical compiler for high level LSI design," Proceedings AFIPS Conference 47, 289-295, June 1978.

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