Section 5 of 5

7.5 Summary

This chapter has described the necessary steps for the fabrication of VLSI circuits. The CAD system must be able to generate manufacturing specifications in a number of different formats, depending on the particular environment of design. Also, interchange formats are a necessary part of a CAD system, to let it communicate with the other systems in the world. This chapter also covered specific implementation issues such as format conversion, testing interface, layout standards, and manufacturing standards. CAD systems and their users should understand these issues in order to complete their task and realize their designs.

Questions

1. Why is there no hierarchy in descriptions of wire-wrap or printed-circuit boards?
2. List three disadvantages of binary file formats.
3. What is the most important feature of any standard output format?
4. List two reasons to convert between output formats.
5. What is the programming-language equivalent of cell libraries? Of design frames?
6. What difficulties may prevent EDIF from becoming a standard?
7. What technological advance will remove the distinction between manufacturing formats and interchange formats?

References

• Borriello, Gaetano; Katz, Randy H.; Bell, Alan G.; and Conway, Lynn, "VLSI System Design by the Numbers," IEEE Spectrum, 22:2, 44-50, February 1985.
• Calma Corporation, GDS II Stream Format, July 1984.
• CMC, Guide to the Integrated Circuit Implementation Services of the Canadian Microelectronics Corporation, version 2:0, Kingston Ontario, January 1986.
• Conway, Lynn; Bell, Alan; and Newell, Martin E., "MPC79: The Demonstration-Operation of a Prototype Remote-Entry Fast-Turnaround VLSI Implementation System," Proceedings MIT Conference on Advanced Research in Integrated Circuits, January 1980 (also reprinted in Lambda, 1:2, 10-19, 2nd Quarter 1980).
• Electronic Design Interface Format Steering Committee, EDIF-Electronic Design Interchange Format Version 1 0 0, Texas Instruments, Dallas, Texas, 1985.
• Factron, "CADDIF Version 2.0 Engineering Specifications," Schlumberger Factron, October 1985.
• Gerber Corporation, "Gerber Format," Gerber Scientific Instrument Company document number 40101-S00-066A, July 1983.
• Gross, A. G.; Raamot, J.; and Watkins, S. B., "Computer Systems for Pattern Generator Control," Bell Systems Technical Journal, 49:9, 2011-2029, November 1970.
• Hellestrand, G. R.; Tan, C. H.; Yong, F. N.; and Forster, R. L., "Australian Multi-Project Chip Activities, 1982-1986", Joint Microelectronics Research Centre, University of New South Wales, October 1986.
• Hon, Robert W. and Sequin, Carlo H., "A Guide to LSI Implementation," 2nd Edition, Xerox Palo Alto Research Center technical memo SSL-79-7, January 1980.
• Johnson, Dean P. and Lipman, Jim, "IC Packaging: An Introduction For the VLSI Designer," VLSI Systems Design, VII:6, 108-116, June 1986.
• Liblong, Breen M., SHIFT-A Structured Hierarchical Intermediate Form for VLSI Design Tools, Masters Thesis, University of Calgary Department of Computer Science, September 1984.
• McCarthy, John; Abrahams, Paul W.; Edwards, Daniel J.; Hart, Timothy P.; and Levin, Michael I., LISP 1.5 Programmer's Manual, MIT Press, Cambridge, Massachusetts, 1962.
• MOSIS, MOSIS User's Manual, University of Southern California Information Sciences Institute, 1986.
• Pieper, Chris, "Stimulus Data Interchange Format," VLSI Systems Design, Part I: VII:7, 76-81, July 1986; Part II: VII:8, 56-60, August 1986.
• VLSI Design Staff, "A Perspective On CAE Workstations," VLSI Design, IV:4, 52-74, April 1985.

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Steven M. Rubin

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